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Dante uses its own digital clocking technology across the Ethernet network to ensure that all Dante devices are synchronized. As part of this logic, an order of priority is defined to identify which device becomes the Dante Master.

A Dante-capable device with a valid BNC Word Clock is chosen as the highest priority, followed by a device with a valid AES3 signal, then SPDIF, then an internally generated clock.

Dante only operates at 48 kHz or 96 kHz, and therefore only uses the Primary Digital Clock to lock the sample rate for the Dante Master.

The Primary Clock on all Dante slaves will be overridden by the Dante Clock. If an additional digital input signal is required on a device that is already a Dante slave, this secondary digital input must be locked using the SRC clock.

The front panel I/O Status View indicates if that device is selected as Dante Clock Master.
Confirmation of Dante Master / Slave status is also displayed in the Lake Controller.